基于DDS的数字移相信号发生器.doc
一、课程设计目的3二、设计任务3三、工作原理及模块分析31、频率预置与调节电路42、累加器43、波形存储器44、D/A转换器5四、相关程序51、加法器51ADD1052ADD3272、存放器81REG10B82REG32B103、ROM124、主程序14五、仿真结果：17六、引脚配置和下载18七、实验心得19一、课程设计目的1、进一步熟悉Quartus 的软件使用方法；2、熟悉利用VHDL设计数字系统并学习LPM_ADD_SUB、LPM ROM、LPM_FF的使用方法；3、学习FPGA硬件资源的使用和控制方法；4、 掌握DDS根本原理，学习利用此原理进展信号发生器的设计二、设计任务完成10位输出数据宽度的频率可调的移相正弦信号发生器，通过按键调节频率和初始相位，实现相位和频率可调的正弦信号发生器三、工作原理及模块分析直接数字频率合成器DDS是通信系统中常用到的部件，利用DDS可以制成很有用的信号源。与模拟式的频率锁相环PLL相比，它有许多优点，突出为1频率的切换迅速；2频率稳定度高。一个直接数字频率合成器由相位累加器、波形ROM、D/A转换器和低通滤波器构成。DDS的原理框图如下所示：图 1 直接数字频率合成器原理图其中K为频率控制字， fc为时钟频率，N为相位累加器的字长，D为ROM数据位及D/A转换器的字长。相位累加器在时钟 fc的控制下以步长K作为累加，输出N位二进制码作为波形ROM的地址，对波形ROM进展寻址，波形ROM输出的幅码Sn经D/A转换器变成梯形波St,再经低通滤波器平滑后就可以得到合成的信号波形了。合成的信号波形形状取决于波形ROM中存放的幅码，因此用DDS可以产生任意波形。本设计中直接利用D/A转换器得到输出波形，省略了低通滤波器这一环节。1、频率预置与调节电路不变量K被称为相位增量，也叫频率控制字。DDS方程为：f0= fc K/2n,f0为输出频率，fc为时钟频率。当K=1时，DDS输出最低频率也既频率分辩率为fc /2nDDS的最大输出频率由 Nyguist 采样定理决定，即fc /2,也就是说K的最大值为2n-1.因此，只要N足够大，DDS可以得到很细的频率间隔。要改变DDS的输出频率，只要改变频率控制字K即可。2、累加器相位累加器的原理图如以下图图 2 相位累加器原理图相位累加器由N为加法器与N位存放器级联构成。每来一个时钟脉冲fc，加法器将频率控制字与存放器输出的累加相位数据相加，再把相加后的结果送至存放器的数据输入端，存放器将加法器在上一个时钟作用后所产生的下数据反响到加法器的输入端；以使加法器在下一个时钟作用下继续频率控制字进展相加。这样，相位累加器在时钟的作用下，进展相位累加，当相位累加器累加满量时，就产生一次溢出，完成一个周期性的动作，这个周期应为 uk= 2n / GCD2N ;k,其中GCD表示最大公约数。3、波形存储器用相位累加器输出的数据作为波形存储器的取样地址进展波形的相位幅值转换，即可在给定的时间上确定输出的波形的抽样幅值。N位的寻址ROM相当于把00- 3600的正弦信号离散成具有2n 样值的序列，假设波形ROM有D位数据位，则2n个样值的幅值以D位二进制数值固化在ROM 中，按照地址的不同可以输出相宜相位的正弦信号的幅值。相位-幅值变换原理图如下所示。图 3 相位-幅度变换原理图4、D/A转换器D/A转换器的作用是把已经合成的正弦波的数字量转换成模拟量，正弦幅度量化序列Sn经D/A转换后变成了包络为正弦波的阶梯波St,S(t)的周期为T=uk*Tc.。需要注意的是，频率合成器对D/A转换器的分辨率有一定的要求，D/A转换器的分辨率越高，合成的正弦波St台阶数就越多，输出 波形的精度也就越高。四、相关程序1、加法器1ADD10LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY lpm;USE lpm.all;ENTITY ADD10 ISPORT(dataa: IN STD_LOGIC_VECTOR (9 DOWNTO 0);datab: IN STD_LOGIC_VECTOR (9 DOWNTO 0);result: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);END ADD10;ARCHITECTURE SYN OF add10 ISSIGNAL sub_wire0: STD_LOGIC_VECTOR (9 DOWNTO 0);PONENT lpm_add_subGENERIC(lpm_direction: STRING;lpm_hint: STRING;lpm_type: STRING;lpm_width: NATURAL);PORT(dataa: IN STD_LOGIC_VECTOR (9 DOWNTO 0);datab: IN STD_LOGIC_VECTOR (9 DOWNTO 0);result: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);END PONENT;BEGINresult <= sub_wire0(9 DOWNTO 0);lpm_add_sub_ponent : lpm_add_subGENERIC MAP(lpm_direction => "ADD",lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",lpm_type => "LPM_ADD_SUB",lpm_width => 10)PORT MAP(dataa => dataa,datab => datab,result => sub_wire0);END SYN;2ADD32LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY lpm;USE lpm.all;ENTITY ADD32 ISPORT(dataa: IN STD_LOGIC_VECTOR (31 DOWNTO 0);datab: IN STD_LOGIC_VECTOR (31 DOWNTO 0);result: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);END ADD32;ARCHITECTURE SYN OF add32 ISSIGNAL sub_wire0: STD_LOGIC_VECTOR (31 DOWNTO 0);PONENT lpm_add_subGENERIC (lpm_direction: STRING;lpm_hint: STRING;lpm_type: STRING;lpm_width: NATURAL);PORT(dataa: IN STD_LOGIC_VECTOR (31 DOWNTO 0);datab: IN STD_LOGIC_VECTOR (31 DOWNTO 0);result: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);END PONENT;BEGINresult <= sub_wire0(31 DOWNTO 0);lpm_add_sub_ponent : lpm_add_subGENERIC MAP(lpm_direction => "ADD",lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",lpm_type => "LPM_ADD_SUB",lpm_width => 32)PORT MAP(dataa => dataa,datab => datab,result => sub_wire0);END SYN;2、存放器1REG10BLIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY lpm;USE lpm.all;ENTITY REG10B ISPORT(clock: IN STD_LOGIC ;data: IN STD_LOGIC_VECTOR (9 DOWNTO 0);q: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);END REG10B;ARCHITECTURE SYN OF reg10b ISSIGNAL sub_wire0: STD_LOGIC_VECTOR (9 DOWNTO 0);PONENT lpm_ffGENERIC (lpm_fftype: STRING;lpm_type: STRING;lpm_width: NATURAL);PORT(clock: IN STD_LOGIC ;q: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);data: IN STD_LOGIC_VECTOR (9 DOWNTO 0);END PONENT;BEGINq <= sub_wire0(9 DOWNTO 0);lpm_ff_ponent : lpm_ffGENERIC MAP(lpm_fftype => "DFF",lpm_type => "LPM_FF",lpm_width => 10)PORT MAP(clock => clock,data => data,q => sub_wire0);END SYN;2REG32BLIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY lpm;USE lpm.all;ENTITY REG32B ISPORT(clock: IN STD_LOGIC ;data: IN STD_LOGIC_VECTOR (31 DOWNTO 0);q: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);END REG32B;ARCHITECTURE SYN OF reg32b ISSIGNAL sub_wire0: STD_LOGIC_VECTOR (31 DOWNTO 0);PONENT lpm_ffGENERIC(lpm_fftype: STRING;lpm_type: STRING;lpm_width: NATURAL);PORT(clock: IN STD_LOGIC ;q: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);data: IN STD_LOGIC_VECTOR (31 DOWNTO 0);END PONENT;BEGINq <= sub_wire0(31 DOWNTO 0);lpm_ff_ponent : lpm_ffGENERIC MAP (lpm_fftype => "DFF",lpm_type => "LPM_FF",lpm_width => 32)PORT MAP(clock => clock,data => data,q => sub_wire0);END SYN;3、ROMLIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY altera_mf;USE altera_mf.all;ENTITY ROM ISPORT(address: IN STD_LOGIC_VECTOR (9 DOWNTO 0);clock: IN STD_LOGIC ;q: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);END ROM;ARCHITECTURE SYN OF rom ISSIGNAL sub_wire0: STD_LOGIC_VECTOR (9 DOWNTO 0);PONENT altsyncramGENERIC(address_aclr_a: STRING;init_file: STRING;intended_device_family: STRING;lpm_hint: STRING;lpm_type: STRING;numwords_a: NATURAL;operation_mode: STRING;outdata_aclr_a: STRING;outdata_reg_a: STRING;widthad_a: NATURAL;width_a: NATURAL;width_byteena_a: NATURAL);PORT (clock0: IN STD_LOGIC ;address_a: IN STD_LOGIC_VECTOR (9 DOWNTO 0);q_a: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);END PONENT;BEGINq <= sub_wire0(9 DOWNTO 0);altsyncram_ponent : altsyncramGENERIC MAP (address_aclr_a => "NONE",init_file => "LUT10*10.MIF",intended_device_family => "Cyclone",lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=NONE",lpm_type => "altsyncram",numwords_a => 1024,operation_mode => "ROM",outdata_aclr_a => "NONE",outdata_reg_a => "CLOCK0",widthad_a => 10,width_a => 10,width_byteena_a => 1)PORT MAP (clock0 => clock,address_a => address,q_a => sub_wire0);END SYN;4、主程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGiC_UNSIGNED.ALL;ENTITY DDS_SIN_YANGTIANJUN_CHENYAOSHUAI IS PORT( CLK: IN STD_LOGIC;-系统时钟FWORD: IN STD_LOGIC_VECTOR(7 DOWNTO 0);-频率控制字PWORD: IN STD_LOGIC_VECTOR(7 DOWNTO 0);-相位控制字FOUT: OUT STD_LOGIC_VECTOR(9 DOWNTO 0);-可移相正弦信号输出POUT: OUT STD_LOGIC_VECTOR(9 DOWNTO 0);CLKOUT:OUT STD_LOGIC);-参考信号输出END DDS_SIN_YANGTIANJUN_CHENYAOSHUAI;ARCHITECTURE one OF DDS_SIN_YANGTIANJUN_CHENYAOSHUAI ISPONENT REG32B -32 位锁存器PORT(clock: IN STD_LOGIC ;data: IN STD_LOGIC_VECTOR (31 DOWNTO 0);q: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);END PONENT;PONENT REG10B -10 位锁存器PORT(clock: IN STD_LOGIC ;data: IN STD_LOGIC_VECTOR (9 DOWNTO 0);q: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);END PONENT;PONENT ADD32 -32位加法器PORT(dataa: IN STD_LOGIC_VECTOR (31 DOWNTO 0);datab: IN STD_LOGIC_VECTOR (31 DOWNTO 0);result: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);END PONENT;PONENT ADD10 - 10位加法器的设计PORT(dataa: IN STD_LOGIC_VECTOR (9 DOWNTO 0);datab: IN STD_LOGIC_VECTOR (9 DOWNTO 0);result: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);END PONENT;PONENT ROM -10位地址10位数据正弦信号数据ROMPORT(address: IN STD_LOGIC_VECTOR (9 DOWNTO 0);clock: IN STD_LOGIC ;q: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);END PONENT;SIGNAL F32B,D32B, DIN32B:STD_LOGIC_VECTOR(31 DOWNTO 0);SIGNAL P10B,LIN10B,SIN10B:STD_LOGIC_VECTOR(9 DOWNTO 0);BEGINCLKOUT<=CLK;F32B(27 DOWNTO 20)<=FWORD;F32B(31 DOWNTO 28)<="0000"F32B(19 DOWNTO 0)<="00000000000000000000"P10B(9 DOWNTO 2)<=PWORD;P10B(1 DOWNTO 0)<="00"u1 : ADD32 PORT MAP(dataa=>F32B,datab=>D32B,result=>DIN32B);u2 : REG32BPORT MAP(q=>D32B,data=>DIN32B,clock=>CLK);u3 : ROM PORT MAP(address=>SIN10B,q=>FOUT,clock=>CLK);u4 : ADD10 PORT MAP(dataa=>P10B,datab=>D32B(31 DOWNTO 22),result=>LIN10B);u5 : REG10B PORT MAP(q=>SIN10B,data=>LIN10B,clock=>CLK);u6 : ROM PORT MAP(address=>D32B(31 DOWNTO 22),q=>POUT,clock=>CLK);END one;五、仿真结果：图4仿真波形由仿真结果来看改变相位和频率输入，相应输出的频率和相位也跟随着相应的变化。故仿真结果正确。六、引脚配置和下载图5引脚配置图6下载图7实际波形经实际硬件验证，可通过按键改变频率和相位的值而改变正弦信号发生器输出波形的频率和相位。七、实验心得实验涉及了对LPM_ADD_SUB、LPM ROM、LPM_FF宏模块的使用、例化方法的使用，完成DDS数字移相信号发生器。实验中需要注意的问题有很多，例如需要保证ROM中的数据要至少1024个，保证正弦信号的完整性；在引脚配置中注意选择16进制的按键和10位D/A的引脚。本实验从设计到仿真验证在到硬件验证，让我们逐步深刻地了解DDS移相信号发生器的原理。
