东南大学信息学院poc实验报告.doc

-puterOrganization andArchitecture COURSEDESIGNA Parallel Output Controller- (POC)Southeast universitySchool of Information Science and Engineering1. Designpurposea. Thepurpose of thisproject isto design and simulate aparallel output controller(POC)which acts an interface between systembus and printer. The ISE 14.7EDAtool isremended and provided for simulation.b. Learnaboutthe using of Bi-directionalData Bus (BDB), anduse a parallel Bi-directional Data Bus to finishthe data transmission betweenCPU and POC.2. IntroductionandTasksPOC is one ofthe most monI/Omodules,namely the paralleloutputcontroller.It plays the roleof an interface between the puter systembus and the peripheralFigure1.SystemstructurediagramAs Fig.1 shows theinnerconnecting of aprinter to the systembus through thePOC. The- munication between POC and the printer iscontrolledby a "handshakeprotocolgiven in Fig.2.Figure2. Thehandshake-timing diagrambetween POCand theprinterThehandshakingprocessisdescribedasfollows:Whentheprinterisreadytoreceiveachar- acter,itholdsRDY=1.ThePOCmustthenholdacharacteratPD(paralleldata)portandproduce apulseattheterminalTR(transferrequest).TheprinterwillchangeRDYto0,takethecharacter. z.-atPDandholdRDYat0untilthecharacterhasbeenprinted(e.g.delay5or10ms),thensetRDY to 1 again when it isready to receive the ne*t character.The buffer register BR is used to temporarily hold a character sent fromthe processor, which char- acter willbe transferred to the printerlater.The status register SRis used for twocontrol functions:SR7servesasareadyflagtoindicatePOCisreadyornottoreceiveanewcharacterfromthe processor.SR0 is used to enable the interruptrequests sent by POC.Ininterruptmode,If SR0=1,thenPOCwillsendaninterruptrequestsignaltoprocessorwhenitis ready to receive a character(i.e., when SR7=1).IfSR0=0, then POC willnot interrupt.The transferofa character to POC via the systembus proceeds asfollows:In interrupt mode, SR0 isalways 1.After sending character to printer, POC sets the SR7 to 1, since SR0=1, the interrupt request signal (IRQ) is set to 0, which indicate an effective interrupt signal to the processor.1、processorsetsthevalueofSR7&setsthe valueofBRWhentheprocessordetectstheeffectiveIRQsignal,theprocessordirectlyselectsBRandwrites acharacterintoBR,(processorwillneverreadthestateofSR7, whichisdifferentwithpollingmode.)ThentheprocessorsetstheSR7to0,whichindicatesthatthenewcharacterhasbeenwrittenintoBR andnot printed yet.2、POCreadsandsetsthevalueofSR7&handshakesoperations withthe printerWhenPOCdetectsthatSR7issetto0,POCthenproceedstostartthehandshakingoperations with theprinter. z.-Aftersendingcharactertoprinter,POCsetstheSR7to1,whichindicatesPOCisreadytoreceive anothercharacterfromtheprocessor.Thetransfercyclecannowrepeat.and aresamewith the polling statePS:DuringthehandshakingoperationsbetweenPOCandprinter,theprocessordoesnottryto access POC until it receivesthe interrupt request signal3. TheoverallconnectionofthesimulatedprinterandPOCe*pressedinthetopmoduleformFigure3.Thetop module formof the project4. DesigndescriptionofthesimulationinputwaveformsThe inputand outputof CPU,POC and printer are shown below:ProcessorjPinsDescriptionInputclkInput the clock for the CPUrunning.modeChoosethemodefor printing.Whenmode=1,select a interrupt mode.IRQReceive the interrupt signal IRQ.When IRQ='1', new datacan be sent.DIN7.0Read data from poc.DOUT7.0Write data into poc.OutputrwShow thedirection of the DOUT7.0 and DIN7.0 When rw='0',read data fromPOC.When 'rw'='1',write datato POC.A0Controlthe address read and write on POC. z.-When A0='0', chooseSR.When A0='1', choose BR.CSCS=1, poc work.data7.0The data send to POC to beprintedPOCPinsDescriptionInputclkInput the clock for the POC running.RWShow thedirection of the DOUT7.0 and DIN7.0 When rw='0',send datato CPU.When'rw'='1',read data fromCPU.A0Input address,When A0='0', chooseBR. When A0='1', choose SR.RDYInput the readysignal fromprinter. When RDY='1', the printer is idle.When RDY='0', the printer is busy.CSInput the mode of the POC.When CS=0,select apolling mode. When CS=1,select a interruptmode.data7.0The data receive fromCPUto be printed.OutputPD7.0Output thedata to printer.IRQOutput theinterrupt signalIRQ to CPU,showingthePOC and printer is ready.TRThe response to print'RDY signal,aone-cycle pulse atthe portTR(transfer request) showsthat newdata is sent toprinter.DOUT7.0CS=0POCsend the stateof SR to CPU;CS=1CPU readthe datawrite in BRSignalSR7.0The register contains the flags for the POC. When SR(7)='1', it's idle.When SR(7)='0', it's busy.BR7.0The register holdsthevalue of datato print.printerPinsDescriptionInputclkInput the clock for the printer running.TRInput the pulse signal fromPOC, to shownewdatais ing.PD7.0Input the data fromPOC.OutputRDYOutput RDY signal,when RDY='1', it shows printer is waiting for newdata. z.-5. SimulationresultsConnection between cpu and pocConnection between poc and printerHere are the e*planationsof the simulation wave:interrupt mode:1、In theinterruptmode,modeis always set1, the print processoccuresby the IRQ signal frompoc.2、When S(7)=0, IRAsend0to cpu, it meansthere is aprint requirement andcpubegin to handle it. 3、Inthe interrupt processRWand A0are singals fromcpu to poc tocontrolthe action ofpoc.RW=1and A0=1writedata fromcpu(D) to poc(BR), means the begin of the interrupt process.RW=*and A0=*means there is no interrupt requirement .4、AftersendingdatastoBRandsetsrto"00000000, if RDY=1,pocgiveaimpulseinTRtomaketheprinter begintowork. AftertheTRsignalwecanseethattheinputRDYsignalfromtheprinterchange from 1 to0, whichshowsthattheTRsignalreallymaketheprinterwork.5、After data of BR has been transmitted into printer,poc setSR to "10000001itself to indicate that it es to ready and can get the ne*t print task.6、Let data plus 1 to indicate the ne*t new print cycle.6. Conclusion and Discussions1、As a parallel output controller ,poc module to act as an interface between cpu and printer. Form the simulation wave, we can see that my program meets the designs requirements.2、I divide the system into three parts, and one top entity. And I use two way to finishthe top entity. One is write program with vhdl language and another is create aschematic type file and connect wire.3、By designing the POC module, I find it helps to learn how to use of quartus and VHDL for design and simulation.The process of designing also teachs me the importantce of figuring out the struc- ture and timing of the task before programming .Appendi*:The program of processor:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;- Unment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Unment the following library declaration if instantiating- any *ilin* primitives in this code.-library UNISIM;-use UNISIM.Vponents.all;entity processor isport(clk : in std_logic;IRQ : in std_logic;DOUT : out std_logic_vector(7 downto 0):="00000000"RW : out std_logic:='0'-0read,1writeA0 : out std_logic:='0'-0sr,1brDIN : in std_logic_vector(7 downto 0);end processor;architecture Behavioral of processor issignal data:std_logic_vector(7 downto 0):="00000000"signal mode:std_logic:='1'-默认为中断模式beginprocess(clk)begin if clk'event and clk='1' thenif mode='1' then if IRQ='0' then A0<='1' RW<='1'-写入数据到BR data<=data+"00000001"-代表传输的字符 DOUT<=data; else A0<='*' RW<='*'-读入SR的数据 end if; end if;end if;end process;end Behavioral;the program of poc:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_arith.ALL;use ieee.std_logic_unsigned.ALL;- Unment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Unment the following library declaration if instantiating- any *ilin* primitives in this code.-library UNISIM;-use UNISIM.Vponents.all;entity poc isport(A0 : in std_logic;RW : in std_logic;clk : in std_logic;CS : in std_logic:='1'RDY : in std_logic;IRQ : out std_logic:='1'DOUT : out std_logic_vector(7 downto 0);PD : out std_logic_vector(7 downto 0);TR : out std_logic:='0'DIN : in std_logic_vector(7 downto 0);end poc;architecture Behavioral of poc issignal SR : std_logic_vector(7 downto 0):="10000001"signal BR : std_logic_vector(7 downto 0):="00000000"signal count:integer range 0 to 5:=0;type state_type is (s0,s1,s2);signal state: state_type:=s0;beginprocess(clk)begin if clk'event and clk='1' then TR<='0' IRQ<='1'case state iswhen s0=>-中断请求信号 if SR(7)='1' then IRQ<='0'-中断请求state<=s1; else IRQ<='1'state<=s2;-无中断请求 end if;when s1=>-读入读出选择 if RW='1' and A0='1' then-cpu写入数据到BR BR<=DIN; SR(7)<='0'state<=s2; elsif RW='0' and A0='0' then-cpu读入SR的数据 DOUT<=SR; elsif RW='1' and A0='0' then-cpu写入数据到SR SR<=DIN; elsif RW='0' and A0='1' then-cpu读入BR的数据 DOUT<=BR; end if;when s2=>-打印机 if RDY='1' then TR<='1' PD<=BR; SR(7)<='1' end if;state<=s0; end case;end if;end process;end Behavioral;the program of printer:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_arith.ALL;use ieee.std_logic_unsigned.ALL;- Unment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Unment the following library declaration if instantiating- any *ilin* primitives in this code.-library UNISIM;-use UNISIM.Vponents.all;entity print isport(RDY : out std_logic:='1'TR : in std_logic;PD : in std_logic_vector(7 downto 0);clk : in std_logic);end print;architecture Behavioral of print issignal count: integer range 0 to 5:=0;signal data: std_logic_vector(7 downto 0);signal ready:std_logic;beginprocess(clk,TR)begin if clk'event and clk='1' then if TR='1' then RDY<='0' ready<='0' data<=PD; else if ready='0' then count<=count+1; if count=5 then RDY<='1' ready<='1' count<=0; end if; end if; end if;end if;end process;end Behavioral;connection program:library IEEE;use IEEE.STD_LOGIC_1164.ALL;- Unment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Unment the following library declaration if instantiating- any *ilin* primitives in this code.-library UNISIM;-use UNISIM.Vponents.all;entity top isport(CLK : in std_logic);end top;architecture Behavioral of top issignal a0:std_logic;signal irq:std_logic;signal d1:std_logic_vector(7 downto 0);signal d2:std_logic_vector(7 downto 0);signal rw:std_logic;signal rdy:std_logic;signal pd:std_logic_vector(7 downto 0);signal tr:std_logic;ponent processorport(clk : in std_logic;IRQ : in std_logic;DOUT : out std_logic_vector(7 downto 0):="00000000"RW : out std_logic:='0'-0read,1writeA0 : out std_logic:='0'-0sr,1brDIN : in std_logic_vector(7 downto 0);end ponent;ponent pocport(A0 : in std_logic;RW : in std_logic;clk : in std_logic;CS : in std_logic:='1'RDY : in std_logic;IRQ : out std_logic:='1'DOUT : out std_logic_vector(7 downto 0);PD : out std_logic_vector(7 downto 0);TR : out std_logic:='0'DIN : in std_logic_vector(7 downto 0);end ponent;ponent printport(RDY : out std_logic:='1'TR : in std_logic;PD : in std_logic_vector(7 downto 0);clk : in std_logic);end ponent;beginu1: processor port map(clk=>CLK,A0=>a0,RW=>rw,IRQ=>irq,DOUT=>d1,DIN=>d2);u2: poc port map(clk=>CLK,A0=>a0,RW=>rw,IRQ=>irq,DOUT=>d2,DIN=>d1,RDY=>rdy,TR=>tr,PD=>pd);u3: print port map(clk=>CLK,RDY=>rdy,TR=>tr,PD=>pd);end Behavioral;. z.