微波炉控制器设计.docx

定时器集成电路的设计一、根本功能1、复位开关：reset2、启动开关：start_cook3、烹调时间设置：setjime4、烹调时间显示：min;sec5、七段码测试：test6、启动输出：cook二、信号描述T、CLK：外部时钟。std_logic;2、 RESET：复位信号，“1有效。StLbgic;3、 TEST:测试信号"1”有效。StdJogic;'4、SETTIME：时间设置"1"有效。std_logic;5、 DATA15.0:4*4BCD数码设置(59分59秒)std_logic_vector(15.0);6、 STRTCOOK：烹调开始“1”有效。StdJogic;1、COOk:烹调进行信号，接继电器“1有效。StdJogic;2、min_msb:3、minsb:4、sec_msb:5、sejlsb:std_logic_vector(1to7);std_logic_vector(1to7);std_logic_vector(1to7);std_logic_vector(1to7);三、设计分析1、控制状态机：工作状态状态转换。2、数据装入电路：根据控制信号选择定时时间、测试数据或完成信号的装入。3、定时器电路：负责完成烹调过程中的时间递减计数和数据译码供应七段数码显示，同时还可以提供烹调完成时间的状态信号供控制状态机产生完成信号。microwave_timer四、模块设计CL. KDONE TE STSE TeTXMERE SE TTfRT.COOKCUK一COOKDONECOOKTE STLORD.8888TLORD.8888SET.TXMEI.OAD_CI_KTL.OAD.CL.KRE SE TL.OAD_DONE-XLOAD_DONESTaT一CoUZTROLSTRRTeOOOK1、控制状态机设计输入输出信号ENTITYstate_countrolISPORT(elk,done,resetJest,set_time,start_cook:INstd_logic;cook,load_8888,load_clk,load_done:OUTstd_logic);END;根据输入信号和自身当时的状态完成状态转换和输出相应的信号。Cook：指示烹调进行中，同时提示计时器减数。load_8888：指示LoADER装入完成测试数据。load_clk：指示LoADER装入设置烹调时间数据。load.done：指示LoADER装入完成信息数据。 状态分析idle:复位状态。IamPjeSt:数码管测试状态。Sejclock:烹调时间设置状态。Timer：减数定时状态。done_msg：完成信息显示状态。 程序设计libraryIEEE;useIEEE.std_logic_1164.aIl;ENTITYstate_countrolISPORT(elk,done,reset,test,set_time,start_cook:INstd_logic;cook,load_8888,load_clk,load_done:OUTstd_logic);END;ARCHITECTUREaOFstate_countrolISTYPESTATE_TYPEIS(idle,lamp_test,set_clock,timer,done_msg);SIGNALnext_state,current_state:STATE_TYPE;BEGINPROCESS(elk,reset)BEGINIFreset=TTHENcurrent_state<=idle;ELSIF(clk'EVENTANDelk=')THENcurrent_state<=next_state;endif;endPROCESS;PROCESS(current_state,set_time,start_cook,test,done)beginnext_state<=idle;load_8888<=,0'load-clk<-0"load-done<='0,;cook<='0'CASEcurrent_stateISWHENlamp_test=>load_8888<="1'next-state<=idle;WHENset_clock=>load_clk<-1,;next-state<=idle;WHENdone_msg=>load_done<='1'next_state<=idle;WHENidle=>iftest='thennext_state<=lamp_test;load_8888<='elsifset_time-thennext_state<=set_clock;load-clk<='elsifstart-cook='1'anddone='0'thennext_state<=timer;cook<-;endif;WHENtimer=>ifdone-thennext_state<=done_msg;load-done<='elsenext_state<=timer;cook<='endif;ENDCASE;ENDPROCESS;ENDa;2、数据装入电路设计 输入输出信号PORT(load_8888,load_clk,load_done:INStdJogic;data:INstdOgiJVeCtOr(15downtoO);load:OUTstd_logic;load_val:OUTstd_logic_vector(15downto0);END;数据装入电路根据输入信号的描述是组合逻辑电路，类似多路选择器。数据装入和输出均为BCD编码。1.OADERLOAD.8888 XLOAD.8888LOADmCLK >L.OAD.CL.KLOADX LORDLORDsDONELORDmDOHELORD.VAUX5. . OJ -"KL,ORDmVRLM TRC IS . . ODATAXS.OJIoaCL8888："1”时，输出测试数据。load_clk：输出设置烹调时间数据。load_done：T输出完成信息数据。load：指示TlMER处于数据装入状态并装入有效数据。程序设计1.ibraryIEEE;uselEEE.stdOgic164.all;useIEEE.std_logic_arith.all;ENTITYloaderISPORT(load_8888,load_clk,load_done:INstd_logic;data:INstdOgijVeCtOr(15downto0);load:OUTstdOgic;load_val:OUTstdOgijVeCtOr(15downto0);END;ARCHITECTUREaOFloaderISBEGINPROCESS(data,load_8888,load_clk,load_done)variabletemp:std_logic_vector(2downto0);BEGINload<=IoaCL8888orload_doneorload_clk;temp:=load_8888&Ioad_done&load_clk;CASEtempISWHEN"100',=>load_val<=alL8;WHEN"010"=>load_val<=done;WHEN"OO,=>Ioad_val<=data;WHENothers=>null;ENDCASE;ENDPROCESS;ENDa;3、定时电路设计 输入输出信号ENTITYtimerISPORT(clk:INstdOgic;data:INstd_logic_vector(15downtoO);down:INstd_logic;load:INstd_logic;done:outstd_logic;min_msb:outstd_logic_vector(1to7);min_lsb:outstd_logic_vector(1to7);sec_msb:outstd_Iogic_vector(1to7);sec_lsb:outstd_Iogic_vector(1to7);END;定时电路根据输入信号的描述是时序逻辑电路，主要由计数器构成。设计方法采用例化设计法。电路具有装入功能、逆计数功能及数据译码功能。1.oad：ii,f时，完成装入功能。down:“1"时,执行逆计数功能。Done：表不宾调完成。min_msbminSbsec_msbsec_lsb：用于驱动七段数码管显示。注意：（1） 需要4个计数器（COImter4）,每个计数器宽度为4。（2） 分、秒在个位“10”进制，在十位上“6进制。如“59分：59秒。timer程序设计1.ibraryIEEE;useIEEE.std_logic_1164.aIl;useIEEE.std_logic_arith.all;useIEEE.std_logic_unsigned.aIl;ENTITYtimerISPORT(clk:INstdOgic;data:INstd_logic_vector(15downtoO);down:INstd_logic;load:INstd_logic;done:outstd_logic;min_msb:outstd_logic_vector(1to7);min_lsb:outstd_logic_vector(1to7);sec_msb:outstd_logic_vector(1to7);sec_lsb:outstd_Iogic_vector(1to7);END;ARCHITECTUREaaOFtimerIScomponentcounter4PORT(clk:INstdogic;cnt_f_5:INStdJogic;data_in:INstd_logic_vector(3downto0);down:INStdJogic;load:INstd_logic;zero:OUTstdOgic;segs:OUTstd_logic_vector(1to7);endcomponent;signalzer,zerl,zer2,zer3:StdJogic;signaldownO,downl,down2,down3:std_logic;signaldata,data1,data2,data3:std_logic_vector(3downtoO);signalis_five,is_nine:std_logic;beginis-five<='1,;is-nine<='O'data3<=data(15downto12);data2<=data(11downto8);datal<=data(7downto4);data<=data(3downtoO);process(zerO,zerl,zer2,zer3,down)begindone<=zer3andzer2andzerlandzer;down3<=,0'down2<='0'down1<='0,;down0<='0,;if(down-)thendownO<='endif;if(zer-)thendownl<='endif;if(zerl-)thendown2<-;endif;if(zer2-)thendown3<-;endif;endprocess;u3:counter4portmap(clk=>clk,cnt_fL5=>is_five,data_in=>data3,down=>down3,load=>load,zero=>zer3,segs=>min-msb);u2xounter4portmap(clk=>clk,cnt_fL5=>is_nine,data_in=>data2,down=>down2,load=>load,zero=>zer2,segs=>min-lsb);ukcounter4portmap(clk=>clk,cnt_fL5=>is_five,data_in=>data1,down=>down1,load=>load,zero=>zerl,segs=>sec-msb);u0xounter4portmap(clk=>clk,cnt_fL5=>is_nine,data_in=>dataO,down=>downO,load=>load,zero=>zerO,segs=>sec-lsb);ENDaa;4、计数电路设计 输入输出信号ENTITYcounter4ISPORT(clk:INStdJogic;INstdOgic;data_in:INstd_Iogic_vector(3downtoO);down:INstd_logic;load:INStdJogic;zero:OUTstdOgic;segs:OUTstd_Iogic_vector(1to7);END;计数电路根据输入信号的描述是时序逻辑电路。电路设计采用“例化”设计方法。具体包括4个需要例化的元件模块：零指示模块(Zero.detect)、译码器模块(bcd7)、减法器模块IdeC4)、双端口装入存放器模块(dual_reg4)ocok：“同步时钟信号。1.oad："1"时，且在时钟为高电平，数据data_in被装入到计数器；否那么，当down为高电平，计数器开始减数。cnt_f_5：进制设置。“1执行六进制、“0执行十进制。down：驱动一个7段数码管。计数器的4位输出经过译码器得到。counter4程序设计1.ibraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.al1;useIEEE.std_logic_unsigned.all;ENTITYcounter4ISPORT(clk:INstd_logic;cnt_f_5:INStdJogic;data_in:INstd_Iogic_vector(3downtoO);down:INstd_logic;load:INStdJogic;zero:OUTstdOgic;segs:OUTstd_Iogic_vector(1to7);END;ARCHITECTUREaOFcounter4IScomponentzero_detectport(a:INstd_logic_vector(3downtoO);zero:OUTstdOgiC);endcomponent;componentbcd7PORT(q:INstd_logic_vector(3downtoO);segments:OUTstd_logic_vector(1to7);endcomponent;componentdec4PORT(cnt_f_5:INStdJogic;dec_in:INstd_Iogic_vector(3downtoO);dec_out:OUTstdOgiJVeCtOr(3downto0);endcomponent;componentdual_reg4PORT(a:INSteUOgiJVeCtOr(3downtoO);b:INstdOgijVeCtOr(3downtoO);elk:INstdOgic;Ida:INstd_logic;ldb:INstd_logic;q:OUTstdOgiJVeCtOr(3downto0);endcomponent;signalcount:std_logic_vector(3downtoO);signaltemp:std_logic_vector(3downtoO);BEGINuO:zero_detectportmap(a=>count,zero=>zero);ukbcd7portmap(q=>count,segments=>segs);u2:dec4portmap(cnt_L5=>cnt_L5,dec_in=>count,dec_out=>temp);u3:dual_reg4portmap(a=>data_in,b=>temp,clk=>clk,lda=>load,ldb=>down,q=>count);ENDa;5、零指示模块(zero-detect)设计NERoDETECTZEROAC3.0.6NEROl×输入输出信号ENTITYzero_detectISPORT(a:INstdOgijVeCtOr(3downtoO);zero:OUTstd_logic);END;该电路根据输入信号的描述是组合电路。程序设计1.ibraryIEEE;useIEEE.std_logic_1164.aIl;ENTITYzero_detectISPORT(a:INstdOgiJVeCtor(3downtoO);zero:OUTstd_logic);END;ARCHITECTUREaOFzero_detectISBEGINzero<='WHENa="0000"else'0'ENDa;6、译码器模块(bcd7)设计BCD7QC3.06EGMWZT*ri.SEGMKMTSI.7J输入输出信号ENTITYbcd7ISPORT(q:INstdOgiJVeCtor(3downtoO);segments:OUTstd_logic_vector(1to7);END;该电路根据输入信号的描述是组合电路。程序设计1.ibraryIEEE;useIEEE.std_logic_1164.all;ENTITYbcd7ISPORT(q:INstdOgiJVeCtor(3downtoO);segments:OUTstd_logic_vector(1to7);END;ARCHITECTUREaOFbcd7ISBEGINprocess(q)BEGINcaseqisWHEN"0000"=>segments<="1111110"WHEN"0001"=>segments<="1100000"WHEN"0010"=>segments<="101101,;WHEN"0011"=>segments<="111001,;WHEN"0100"=>segments<="1100101"WHEN"0101"=>segments<="011011,;WHEN"0110',=>segments<="011111,;WHEN"0111"=>segments<="l100010h;WHEN,'1000"=>segments<="111111,;WHEN"1001"=>segments<="111011,;WHEN"1010"=>segments<="111100,;WHEN,'1011"=>segments<="011100,;WHEN,'11OO',=>segments<="0101001"WHEN"1101',=>segments<=,'0011111"WHENothers=>segments<="0000000"endcase;endprocess;ENDa;7、减法器模块(dec4)设计stdOgic;std_logic_vector(3 downto 0);stdOgijVeCtOr(3 downto 0); 输入输出信号ENTITYdec4ISPORT(cnt_f_5:INdec_in:INdec_out:OUTEND;该电路根据输入信号的描述是组合电路。程序设计1.ibraryIEEE;useIEEE.std_logic_1164.aIl;useIEEE.std_logic_arith.all;uselEEE.stdOgiC_unsigned.all;ENTITYdec4ISPORT(cnt_f_5:INstdOgic;dec_in:INstd_logic_vector(3downtoO);dec_out:OUTstdOgiJVeCtor(3downto0);END;ARCHITECTUREaOFdec4ISsignalmaxval:std_logic_vector(3downtoO);BEGINmaxval<="0101"WHENcnt_L5='else"100,;dec_out<=maxvalWHENdec_in="OOOO"elsemaxval-1;ENDa;8、双端口装入存放器模块IdIIaLreg4)设计DiJal_REG4R3.03BC3.0JCt-KQ3.0JUDA1.DB 输入输出信号ENTITYdual_reg4ISPORT(a: INstdOgijVeCtOr(3downtoO);b: INstdOgiJVeCtor(3downtoO);elk:INstdOgic;Ida:INstdOgic;ldb:INstdOgic;q:OUTstdOgiJVeCtOr(3downto0);END;该电路根据输入信号的描述是时序电路。程序设计1.ibraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.all;useIEEE.std_logic_unsigned.aIl;ENTITYdual_reg4ISPORT(a:INstdOgijVeCtOr(3downtoO);b:INstdOgiJVeCtOr(3downtoO);elk:INstd_logic;Ida:INstd_logic;ldb:INstdOgic;q:OUTstdOgiJVeCtOr(3downto0);END;ARCHITECTUREaOFdual.reg4ISBEGINprocess(clk)beginifclk'eventandelk-thenif(lda-)thenq<=a;elsif(ldb-)thenq<=b;endif;endif;endprocess;ENDa;9、主电路IniCro*ave_timer设计OLKRESET>TESTMI：CROWaVE.TIMERRESET>-ORTRCX5.0TESTCOOKMXN.L.SBCX.SEC.MSBX.MINsMSBCX.7J-CSEC_MSBXSETeTIME>SETeTIMESEO.i-SBX.7J三XSECmLSBCXSTART-COOK>startmcook输入输出信号ENTITYmicrowave_timerISPORT(clk:INStdJogic;reset:INStdJogic;data:INstdOgiJVeCtOr(15downtoO);test:INstd_logic;set_time:INstd_logic;start_cook:INstd_logic;cook:outstd_logic;min_msb:outstd_logic_vector(1to7);minjsb:outstd_logic_vector(1to7);sec_msb:outstd_Iogic_vector(1to7);sec_lsb:outstd_logic_vector(1to7);END;总体电路根据输入信号的描述是时序电路。由三大模块构成：控制状态机(state_countrol)：工作状态状态转换。数据装入电路(loader)：根据控制信号选择定时时间、测试数据或完成信号的装入。定时器电路(timer)：负责完成烹调过程中的时间递减计数和数据译码供应七段数码显示，同时还可以提供烹调完成时间的状态信号供控制状态机产生完成信号。总体设计方法：(1) 时序电路设计、组合电路设计。(2) 状态机电路设计、多层例化电路设计。microwave-timer主程序microwave_timer设计1.ibraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.all;useIEEE.std_Iogic_unsigned.aII;ENTITYmicrowave_timerISPORT(clk:INStdJogic;reset:INstd_logic;data:INstd_logic_vector(15downtoO);test:INstd_logic;set_time:INStdJogic;start_cook:INstd_logic;cook:outstd_logic;min_msb:outstd_logic_vector(1to7);min_lsb:outstd_logic_vector(1to7);sec_msb:outstd_Iogic_vector(1to7);sec_lsb:outstd_Iogic_vector(1to7);END;ARCHITECTUREaaOFmicrowave_timerIScomponentstate_countrolPORT(elk,done,reset,test,set_time,start_cook:INstd_logic;cook,load_8888,load_clk,load_done:OUTstd_logic);endcomponent;componentloaderPORT(load_8888,Ioad_clk,load_done:INstd_logic;data:INstdOgiJVeCtOr(15downtoO);load:OUTstd_lOgic;load_val:OUTstdOgiJVeCtOr(15downto0);endcomponent;componenttimerPORT(clk:INStdJogic;data:INstd_logic_vector(15downtoO);down:INStdJogic;load:INstd_logic;done:outstd_logic;min_msb:outstd_logic_vector(1to7);min_lsb:outstd_Iogic_vector(1to7);sec_msb:outstd_Iogic_vector(1to7);sec_lsb:outstd_logic_vector(1to7);endcomponent;signaldata_tmp:std_logic_vector(15downtoO);signalcook_tmp:std_Iogic;signalload_8888:std_logic;signalload_clk:StdJogic;signalload_done:std_logic;signalload:std_Iogic;signaldown:std_logic;signaldone:StdJogic;begincook<=cook-tmp;uO:state_countrolportmap(clk=>clk,done=>done,reset=>reset,test=>test,set_time=>set_time,start_cook=>start_cook,cook=>cook_tmp,load_8888=>load_8888,load_clk=>load_clk,load_done=>load_done);ukloaderportmap(load_8888=>load_8888,load_clk=>load_clk,load_done=>load_done,data=>data,load=>load,Ioad_val=>data_tmp);u2:timerportmap(clk=>clk,data=>data_tmp,down=>cook_tmp,load=>load,done=>done,min_msb=>min_msb,min_lsb=>min_lsb,sec_msb=>sec_msb,sec_lsb=>sec_lsb);ENDaa;