pci引脚定义pci接口定义.doc

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1、-pci引脚定义Pin+5V+3.3VUniversalDescriptionA1TRSTTest Logic ResetA2+12V+12 VDCA3TMSTest Mde SelectA4TDITest Data InputA5+5V+5 VDCA6INTAInterrupt AA7INTCInterrupt CA8+5V+5 VDCA9RESV01Reserved VDCA10+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)A11RESV03Reserved VDCA12GND03(OPEN)(OPEN)Ground or Open (Key)A13G

2、ND05(OPEN)(OPEN)Ground or Open (Key)A14RESV05Reserved VDCA15RESETResetA16+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)A17GNTGrant PCI useA18GND08GroundA19RESV06Reserved VDCA20AD30Address/Data 30A21+3.3V01+3.3 VDCA22AD28Address/Data 28A23AD26Address/Data 26A24GND10GroundA25AD24Address/Data 24A26IDSELIni

3、tialization Device SelectA27+3.3V03+3.3 VDCA28AD22Address/Data 22A29AD20Address/Data 20A30GND12GroundA31AD18Address/Data 18A32AD16Address/Data 16A33+3.3V05+3.3 VDCA34FRAMEAddress or Data phaseA35GND14GroundA36TRDYTarget ReadyA37GND15GroundA38STOPStop Transfer CycleA39+3.3V07+3.3 VDCA40SDONESnoop Don

4、eA41SBOSnoop BackoffA42GND17GroundA43PARParityA44AD15Address/Data 15A45+3.3V10+3.3 VDCA46AD13Address/Data 13A47AD11Address/Data 11A48GND19GroundA49AD9Address/Data 9A52C/BE0mand, Byte Enable 0A53+3.3V11+3.3 VDCA54AD6Address/Data 6A55AD4Address/Data 4A56GND21GroundA57AD2Address/Data 2A58AD0Address/Dat

5、a 0A59+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)A60REQ64Request 64 bit A61VCC11+5 VDCA62VCC13+5 VDCA63GNDGroundA64C/BE7*mand, Byte Enable 7A65C/BE5*mand, Byte Enable 5A66+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)A67PAR64Parity 64 A68AD62Address/Data 62A69GNDGroundA70AD60Address/Data 60A71AD58Address

6、/Data 58A72GNDGroundA73AD56Address/Data 56A74AD54Address/Data 54A75+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)A76AD52Address/Data 52A77AD50Address/Data 50A78GNDGroundA79AD48Address/Data 48A80AD46Address/Data 46A81GNDGroundA82AD44Address/Data 44A83AD42Address/Data 42A84+5V+3.3VSignal Rail+V I/O (+5 V

7、or +3.3 V)A85AD40Address/Data 40A86AD38Address/Data 38A87GNDGroundA88AD36Address/Data 36A89AD34Address/Data 34A90GNDGroundA91AD32Address/Data 32A92RESReservedA93GNDGroundA94RESReservedB1-12V-12 VDCB2TCKTest ClockB3GNDGroundB4TDOTest Data OutputB5+5V+5 VDCB6+5V+5 VDCB7INTBInterrupt BB8INTDInterrupt D

8、B9PRSNT1ReservedB10RES+V I/O (+5 V or +3.3 V)B11PRSNT2B12GND(OPEN)(OPEN)Ground or Open (Key)B13GND(OPEN)(OPEN)Ground or Open (Key)B14RESReserved VDCB15GNDResetB16CLKClockB17GNDGroundB18REQRequestB19+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)B20AD31Address/Data 31B21AD29Address/Data 29B22GNDGroundB23A

9、D27Address/Data 27B24AD25Address/Data 25B25+3.3V+3.3VDCB26C/BE3mand, Byte Enable 3B27AD23Address/Data 23B28GNDGroundB29AD21Address/Data 21B30AD19Address/Data 19B31+3.3V+3.3 VDCB32AD17Address/Data 17B33C/BE2mand, Byte Enable 2B34GND13GroundB35IRDYInitiator ReadyB36+3.3V06+3.3 VDCB37DEVSELDevice Selec

10、tB38GND16GroundB39LOCKLock busB40PERRParity ErrorB41+3.3V08+3.3 VDCB42SERRSystem ErrorB43+3.3V09+3.3 VDCB44C/BE1mand, Byte Enable 1B45AD14Address/Data 14B46GND18GroundB47AD12Address/Data 12B48AD10Address/Data 10B49GND20GroundB50(OPEN)GND(OPEN)Ground or Open (Key)B51(OPEN)GND(OPEN)Ground or Open (Key

11、)B52AD8Address/Data 8B53AD7Address/Data 7B54+3.3V12+3.3 VDCB55AD5Address/Data 5B56AD3Address/Data 3B57GND22GroundB58AD1Address/Data 1B59VCC08+5 VDCB60ACK64Acknowledge 64 bit B61VCC10+5 VDCB62VCC12+5 VDCB63RESReservedB64GNDGroundB65C/BE6*mand, Byte Enable 6B66C/BE4*mand, Byte Enable 4B67GNDGroundB68A

12、D63Address/Data 63B69AD61Address/Data 61B70+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)B71AD59Address/Data 59B72AD57Address/Data 57B73GNDGroundB74AD55Address/Data 55B75AD53Address/Data 53B76GNDGroundB77AD51Address/Data 51B78AD49Address/Data 49B79+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)B80AD47Address/Data 47B81AD45Address/Data 45B82GNDGroundB83AD43Address/Data 43B84AD41Address/Data 41B85GNDGroundB86AD39Address/Data 39B87AD37Address/Data 37B88+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)B89AD35Address/Data 35B90AD33Address/Data 33B91GNDGroundB92RESReservedB93RESReservedB94GNDGroundpci 接口定义. z.